1. Field of the Invention
The present invention relates to a switch circuit, and particularly to a discharge circuit for a high-voltage switch circuit.
2. Description of the Prior Art
A high-voltage switch circuit is conventionally used in programmable integrated circuits, such as flash memory devices, for propagating a high voltage to word lines or source lines in order to perform programming or erasing function. FIG. 1 shows a schematic diagram illustrating a typical high-voltage switch circuit 10 conventionally used in flash memory devices. Switch signals SW1 and SW2 are generally global signals, which are used to control switch transistors N6 and N7, respectively, along with other similar transistors, for example, of the same row of the flash memory cell array. Generally, the switch signal SW1 is the inverse of the other switch signal SW2. In this diagram, the output terminals of the switch transistors N6 and N7, designated as OUT1 and OUT2 are coupled to a source line or a word line (not shown). Under the control of the switch transistors N6 and N7 with the signals SW1 and SW2, a high voltage source HV1, which is a global high voltage source generated by a pumping circuit (not shown), can be propagated to the output terminal OUT1 or OUT2. In order to effectively transmit the high voltage HV1 to node D, a local pumping circuit 102 is used to pump (or raise) the voltage level at node C. A two-stage cascade pumping circuit 102 such as that shown in FIG. 1 is usually used, in which clock signal pair of CLK and CLKn (inverted CLK) is provided as a pumping clock pair.
During circuit operation, considering the switch signal SW1 being, at high voltage level and the output terminal OUT1 being connected to the ground, there is a discharge path from node A through nodes B, C and D to the ground. The situation mentioned above is usually referred to as being unselected, compared to a selected situation wherein the voltage potential at the output terminal OUT1 is high. Concerning the unselected situation, the nodes A, B, and C will not be pumped to high voltage. Further, with the transistors N5 and N6, the voltage of the node C will remain zero no matter how the clock CLKn changes. It is worth noting that the passing gate N0 in the switch circuit 10 will not conduct be cause of the zero voltage at the node C, therefore prohibiting the high voltage HV1 from propagating to the output terminal OUT1.
Accordingly, the node A becomes almost floating, and therefore the voltage level of the node A will unwontedly vary with the change of the clock CLK. More specifically, when the clock CLK rises, the node A will be coupled through the capacitor K1, and the voltage at the node A rises a little above zero; when the clock CLK falls, the node A will also be coupled through the capacitor K1, and the voltage at the node A then falls a little below zero. A simulation result of the high voltage sources HV1 and HV2 is shown in FIG. 2. Due to the fact that the node C remains zero as discussed above, the negative voltage at the node A will weakly turn on the transistor N1, thereby sinking some current from another high voltage source HV2 and affecting its pumping circuit (not shown). As the number of the memory cells and their corresponding switch circuits is more than hundreds of thousand, the total sum of these sink currents becomes significant and intolerable, thereby degrading the pumping efficiency of the pumping circuit of the high voltage source HV2, or even failing the programming and erasing function in the flash memory devices. Therefore, a need has been arisen to provide a scheme for overcoming these deficiencies.